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The arithmetic multiplier in T0 is the brainchild of Ph. student Brian Kingsbury, who implemented the 16-bit x 16-bit integer, single cycle unit.The 32-bit result from the multiplier matches the 32-bit width of the other vector functional units including adders, shifters and the vector register file.He has since taken a position as a VLSI designer at Integration Associates in Mountain View, California.

The progress of the debugging and system integration process can be followed via the ICSI world wide web page at:

This performance is somewhat higher than ICSI currently achieves using a four-board Ring Array Processor for the same problem (ICSI's Winter 1989 Newsletter featured an article on the RAP board).

The core design team that "realized" T0 include Asanovic, Brian Kingsbury and Bertrand Irissou, all students of U. Berkeley Computer Science Professor John Wawrzynek. Each team member contributed his unique experience to the project.

To mark the end of the design phase, the three chip designers were honored at a Realization Group lunch on March 15.

Krste Asanovic, Brian Kingsbury and Bertrand Irissou were presented with plaques marking their achievements.

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